Impact of Non-linear Shunts from Pinholes on Device Performance
Pascal Kaienburg a, Paula Hartnagel a, Bart E. Pieters a, David Grabowski a, Jiaoxian Yu a, Thomas Kirchartz a b
a Forschungszentrum Jülich, Institute of Energy and Climate Research, IEK-5 Photovoltaics, Wilhelm-Johnen-Straße, Jülich, Germany
b University of Duisburg-Essen and CENIDE, Faculty of Engineering, Duisburg, Germany
International Conference on Hybrid and Organic Photovoltaics
Proceedings of International Conference on Hybrid and Organic Photovoltaics (HOPV18)
Benidorm, Spain, 2018 May 28th - 31st
Organizers: Emilio Palomares and Rene Janssen
Oral, Pascal Kaienburg, presentation 112
DOI: https://doi.org/10.29363/nanoge.hopv.2018.112
Publication date: 21st February 2018

Pinholes are detrimental to solar cell performance and critical to many inorganic solution-processed materials. For the prominent example of polycrystalline perovskites, optimized processing routes for homogeneous layers have been reported but it is so far unclear if up-scaled wet-chemical fabrication can keep up with the high-quality morphologies achieved by spin-coating in the lab. For other new materials that are still in an early stage of technology development, such as sulfur-based absorbers, the issue of pinholes often remains unsolved. It is therefore important to develop device models that describe the impact of pinholes in the absorber layer on solar cell performance. Shunts from pinholes in the absorber layer are often thought of as an ohmic resistor. In reality a pinhole gives way to an interface between the semiconducting electron and hole transport layers which form a heterojunction with a diode-like and clearly non-linear current-voltage characteristic.

In this work, we first illustrate the fundamentally different effect of non-linear compared to linear shunts on the J-V characteristic. As an example, linear shunts will only affect the open‑circuit voltage Voc if the fill factor FF has already decreased towards 25% while non‑linear shunts can cause a loss in Voc when FF values are still acceptable. For typical layer stacks, we obtain the J-V characteristic of pinholes experimentally by fabricating absorber‑free devices. We then use numerical simulations where we assign the pinhole characteristic to a small area of the solar cell while the rest is assumed to be an ideal photo-generating diode. This approach allows us to investigate the impact of pinholes on device efficiency, FF and Voc. We use a simple effective zero-dimensional parallel circuit model which is verified for a range of relevant parameters by simulations of two-dimensional diode networks. We compare different interlayer combinations that are commonly used in the context of perovskite and other solution‑processed solar cells. We find that certain combinations of electron and hole transport layers like TiO2/spiro-OMeTAD limit the negative impact of shunts from pinholes much more than others like PEDOT:PSS/PCBM. The robustness towards shunts from pinholes should thus be considered a new design criterion for the choice of interlayers in solution-processed thin-film solar cells.

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