Artificial neural networks (ANNs) are composed of nodes (neurons) and edges (synapses), in which the weighted sum of inputs plays a central role in intelligent tasks. Memristors have been the core elements in the physical implementation of multiply-and-accumulate (MAC) operations for ANNs, where they store synaptic weights in either analog (multiple values) or digital (binary values) form. However, such a weight representation may not be the most feasible approach for incorporating such devices into an ANN or deep neural network, especially given that the MAC arrays are prone to various forms of noise even with write-and-verify algorithms and error-tolerant operational methods. Besides, most of the peripheral circuits in the ANN hardware still operate in digital form, so the overhead of converting analog outputs to digital values and digital values to analog inputs is a significant issue. 

This presentation reviews what else can be done with the new memristor functionality. It first classifies the application fields into two categories with edge and node representations. For edge applications, it discusses reservoir computing kernels that enrich input information by projecting the original data into hyperdimensional spaces. More recent forward-forward learning methods, which may eliminate several issues associated with conventional backpropagation, are also introduced. Another interesting field is the application of specialized memristive hardware to NP-hard problems in graphics, such as protein folding, where the underlying physical laws greatly aid in finding optimal solutions. For the node applications, the principles and issues of probabilistic-bit (p-bit) devices are introduced and discussed. In this case, the computationally hard problems are mapped onto the coupler network, and node-state (or spin-state) optimization is performed based on the Ising or Potts Hamiltonian. The general and critical issues in such energy-based optimization include reaching the global minimum, where the noisy responses of the memristive p-bits are helpful. Still, their practical implications, compared with the software solution, require careful evaluation of accuracy, power consumption, and time-to-solution, while accounting for peripheral circuits. The successful implementation of these new hardware requires careful design-technology co-optimization between the algorithm, circuit design, and technology sectors.

Neuromorphic computing based on memristors and memtransistors has gained increasing interest, with two-dimensional (2D) molybdenum ditelluride (MoTe₂) emerging as a promising material due to its low phase-transition energy barrier and tunable electrical properties. Despite these advantages, the relatively narrow memory window of pristine MoTe₂ devices has limited their analog switching performance and neuromorphic functionality. In this talk, I demonstrate a post-processing strategy to enhance the analog switching behavior of lateral MoTe₂ devices through two sequential steps: laser treatment followed by atomic layer deposition of Al₂O₃. This combined approach led to a 70-fold increase in dynamic range in the memristor mode and a 20-fold increase in the memtransistor mode. As a result, artificial neural network simulations exhibited a 10-fold improvement in pattern recognition accuracy. Furthermore, the ability of the devices to operate as both memristors and memtransistors enabled the emulation of both homosynaptic and heterosynaptic plasticity, highlighting their potential for neuromorphic computing applications.

Graph data provides an essential framework for describing complex systems in which the relationships between data points are as important as the data itself. However, conventional graph analysis often requires intensive computation because graph connectivity must be repeatedly searched and updated in software. This work presents a hardware-based computing methodology for graph data analysis using crossbar array structures and memory devices. In the proposed approach, graph nodes and edges are physically mapped onto a crossbar array by controlling the device characteristics in diagonal and non-diagonal regions. Because electrical current naturally flows through paths with lower resistance, the crossbar array can directly evaluate graph connectivity and identify efficient paths in the form of circuit responses. This physical representation of graph structures enables graph-processing functions to be performed at the hardware level, reducing computational overhead and offering a promising route toward next-generation computing systems for complex graph data analysis.

The rapid development of artificial intelligence in the big data era has increased the demand for solving complex combinatorial optimization problems (COPs) such as vehicle routing problem (VRP), which are difficult to efficiently handle with conventional von-Neumann computing systems. Quantum computing, which utilizes quantum bits (qubits) based on the superposition of spin, shows potential for solving COPs. However, the requirement of cryogenic operating environments—necessary for noise elimination and accurate spin detection—remains a significant drawback. To address these challenges, probabilistic computing (P-computing) has recently been proposed as an alternative approach to emulate quantum supremacy even at room temperature.

Here, we showed probabilistic bits (P-bits) with a novel Ti/SiO_x/Ti stack, which is a fundamental building block for P-computing. The SiO_x layer typically exhibits reliable TS behavior, resulting in robust voltage oscillations. When a Ti scavenging layer was introduced at the interface, oxygen vacancies were provided to the SiO_x, causing oscillation to occur probabilistically. Through physical analysis and numerical calculations considering the charging and discharging process, we investigated the underlying mechanism of P-bit operation in the Ti/SiO_x/Ti stack. This results in a sigmoidal probability curve for ‘1’ over a wide range of input voltage. Finally, we verified that leveraging the developed SiO_x-based P-bit can significantly accelerate the algorithm for finding the optimal path in the vehicle routing problem through MATLAB simulation.

Processing-in-memory alleviates the conventional von Neumann bottleneck, but peripheral conversion between analog and digital domains remains a major source of energy and area overhead. Here, we report a signal-domain-conversion-free physical computing platform based on a Spiking Hopfield Network (SHN) implemented with NbO_x-based selector-only Mott memory (SOMM) cells. The SOMM cell monolithically couples non-volatile synaptic resistance with volatile neuronal dynamics within a single device, allowing analog memory states to be directly converted into multi-bit digital outputs through spike counting. This intrinsic transduction from resistance states to spike counts eliminates the need for energy-intensive peripheral conversion stages. By selectively configuring the stochastic and deterministic programming/readout dynamics of the SHN, we implement two representative physical computing primitives with contrasting hardware requirements on the same platform: a physical unclonable function (PUF) and a simulated annealer (SA). The PUF achieves a vast challenge-response pair space of 2^N-1 in an N-cell array, with efficient concealability and reconfigurability, while the SA achieves a 10⁵-fold reduction in energy consumption compared with state-of-the-art GPUs. Overall, we demonstrate that the SHN platform performs computing in a single signal domain without conversions, offering a promising route toward next-generation physical computing architecture.

Memristive devices are promising for next-geneartion nonvolatile memory and neurmorphic computing. Their resistive switching (RS) behavior enables information storage and analog conductance modulation in compact device structures [1,2]. Two-dimensional (2D) materials such as molybdenum disulfide (MoS₂) provide an attractive switching medium for filamentary RS. Their layered structure, van der Waals (vdW) interface, structural anisotropy, and defects can strongly affect ion migration and conductive filament (CF) formation and rupture [3,4]. Here, we discuss recent progress in MoS₂-based filamentary memristive devices, spanning lateral and vertical architectures to wafer-scale fabrication and nanoscale complementary metal-oxide-semiconductor (CMOS)-integratgion.

In lateral silver (Ag)/MoS₂/palladium (Pd) devices based on metal-organic chemical vapor deposition (MOCVD)-grown multilayer MoS₂, forming-free volatile RS was achieved in structures with sub-2µm electrode gaps. The switching is driven by Ag ion migration and occurs at low voltages of ~2 V, with switching times down to 130 ns. A physics-based compact model, supported by density functional theory, connects ion migration with electron transport. This model enables circuit-level simulation of artificial-neuron behavior [5]. In related to sub-µm lateral devices, volatile and nonvolatile switching were obtained in the same MoS₂ device by adjusting the current compliance (cc). These devices showed ON/OFF ratios above 10⁴ and synaptic functions including short- and long-term plasticity [6]. Operando transmission electron microscopy (TEM) of lateral Ag/MoS₂/Pd devices further confirmed the filamentary switching mechanism. It directly visualized Ag CF formation and dissolution along MoS₂ surface, bundles, and vdW gaps under bias [7].

The device studies were then extended to vertical devices with SiO_x/vertically aligned MoS₂ (VAMoS₂) heterostructures. VAMoS₂ was synthesized by sulfurizing Mo thin films in a CVD system, controlling the MoS₂ orientations from lateral to vertical. In this vertical stack, the vdW gaps in VAMoS₂ act as preferential ion-migration pathways between the top and bottom electrodes. These heterostructure devices exhibited low-voltage threshold switching near 0.6 V, fast switching times of ~310 ns, and endurance beyond 10⁴ cycles. TEM analysis revealed residual Ag traces in the high-resistance state after cycling, while a physic-based dynamical model helped clarify the switching kinetics [8]. The SiO_x/VAMoS₂ devices showed reduced cycle-to-cycle variability compared with SiO_x-only reference devices. This improvement indicates that vertically aligned vdW gaps can guide confined filament formation and enhance switching reliability [9], as further supported by variability-aware modeling [10].

For scalability, wafer-scale vertical memristors based on MOCVD-grown multilayer MoS₂ were demonstrated. These devices showed cc-dependent Ag filament evolution, where vertical and lateral filament growth produced intermediate resistance states useful for analog synaptic weight modulation and microsecond-scale current response [11]. Finally, nanoscale MoS₂ memristors were integrated into the back-end-of-line of silicon CMOS microchips in a one-transistor-one-resistor architecture. With an active area of approximately 0.015 um², the cells exhibited forming-free nonvolatile switching at ~0.23 V for SET and ~-0.1 V for RESET. They also showed reproducible operation and low cycle-to-cycle variability. TEM confirmed Ag-based CF formation in the MoS₂ switching layer [12].

Overall, these studies show that combining switching-mechanism analysis, material-structure design, wafer-scale processing, and CMOS integration can advance MoS₂-based filamentary memristors toward scalable and energy-efficient 2D memory and neuromorphic hardware.

Photo-iontronics, defined as the synergistic interplay among electrons, ions, and light, offers
unique opportunities for designing multifunctional devices for next-generation neuromorphic
computing hardware. Mixed electronic-ionic semiconductors, particularly metal halide
perovskites, challenge conventional optoelectronic paradigms through their unique
combination of exceptional optoelectronic properties and intrinsic ionic conductivity.1 While
ion migration is often regarded as detrimental to device stability, it also enables new
functionalities, opening exciting directions for photo-iontronic devices. By integrating ionic
conduction with optoelectronic responses, photo-iontronics could provide a platform for self-
powered, energy-efficient, and neuromorphic device architectures.
In this talk, I will discuss ionic conduction in halide perovskite-based optoelectronics, covering
both lead-based and lead-free perovskite materials.1, 2 By exploiting the coupled ionic and
optoelectronic properties of these materials, we have developed device architectures that
integrate energy harvesting and energy storage within a single platform.3 Furthermore, I will
present a three-terminal electrolyte-gated perovskite optoelectronic device capable of operating
as switchable OR, AND, and universal NOR logic gates.4 In this architecture, the migration of
electrolyte ions, controlled by the gate voltage, induces surface polarization that dynamically
modulates the conductivity of the perovskite channel. Finally, I will provide an outlook on
photo-iontronics as a promising platform for multifunctional devices toward in-sensor
computing.

With the exponential growth of artificial intelligence, big data, and the internet of things, there is an urgent need for high-speed, energy-efficient computing technologies. Neuromorphic computing meets this demand by utilizing hardware architectures capable of massively parallel processing with ultra-low power consumption. Such architectures have traditionally been based on complementary metal-oxide semiconductor circuits; however, scaling up computational performance now requires emerging devices that deliver high-order complexity while remaining highly area- and energy-efficient [1]. Recently, optoelectronic devices based on organic semiconductor and two-dimensional (2D) halide perovskite have emerged for neuromorphic computing due to their attractive optoelectronic properties and low-cost processability. By coupling the high photosensitivity of 2D halide perovskite and good charge transport of organic semiconductors, the resulting interface heterojunction allows for the highly tunable optical modulation of charge-trapping effects, ultimately realizing a robust, nonvolatile photomemory [2]. Herein, a nonvolatile memory device based on a 2D Ruddlesden-Popper-phase perovskite and a p-type organic semiconductor heterojunction is fabricated. The synergy of this heterojunction is critical: the organic layer serves as the primary charge transport channel, while the 2D perovskite’s intrinsic quantum well acts as a charge-trapping layer to capture and store carriers under applied bias. The carrier transport and storage properties during optical gating are optimized, and the memory properties can be readily modulated. The memory device exhibits hysteresis transfer curves with a memory window of 30 V and a current switching ratio of 10³. The results validate the potential of 2D perovskite as a highly effective charge-storage medium, paving the way for fast, low-power optical multi-bit storage for future neuromorphic computing systems.

 Halide perovskite memristors are a promising platform for neuromorphic memory because their switching behavior arises from coupled ionic and electronic processes. These dynamic responses enable rich hysteretic memory functions, but uncontrolled ion migration can also lead to stochastic switching and limit the reliability. The central challenge is therefore to control ionic dynamics while preserving their functional role in memory operation.

 Here, we show two complementary strategies to control ion mediated switching in halide perovskite memristors. Through interfacial engineering, stochastic filamentary pathways are suppressed, leading to forming free programmable switching governed by interfacial ionic accumulation and barrier modulation.[1] Through compositional engineering, lead free perovskite devices exhibit low voltage resistive switching, where analysis of time dependent responses reveals the underlying ionic dynamics and enables extraction of key physical parameters governing hysteresis. [2]

 This work highlights that mobile ion can serve not only a source of instability, but also as controllable internal state variables for neuromorphic memory. By combining compositional design, interfacial engineering, and physical interpretation of hysteresis, halide perovskite memristors provide a versatile route toward programmable ion coupled electronic memory devices.

Artificial vision systems are increasingly central to edge intelligence, yet they often suffer from high data latency and energy consumption due to sensor-processor separation. In-sensor computing (ISC) provides a promising solution by integrating sensing and computation. However, current ISC devices remain constrained by scalability, uniformity, and processability. Here, we address these limitations via a reconfigurable perovskite-photovoltaic platform that can be facilely processed from solutions. This architecture allows precise, reconfigurable photoresponsivity tuning with ultra-low variability and supports fabrication on both rigid and flexible substrates. The device exhibits up to ±1120 mA W⁻¹ photoresponsivity and 1000 programmable states, with excellent air stability (30 days) and thermal reliability (80 °C). The scalability of these devices is demonstrated via a proof of concept 32×32 array. The excellent uniformity and programmability of the array are utilized in energy-efficient face detection applications (achieving 95.2% sensitivity and 4.51× speedup for subsequent computation) in addition to image feature extraction and MNIST digit recognition tasks (96.97% accuracy). Compared to previous ISC implementations, our system offers enhanced tunability, fabrication scalability, and functional stability. These results establish a practical perovskite-based ISC platform, offering new avenues for intelligent computing systems in robotics, wearable electronics, and neuromorphic vision.^[1]

Electrochemical random-access memory (ECRAM) is a promising synaptic device for analog in-memory computing because its conductance can be gradually modulated through ionic motion. While ECRAM linearity and symmetry are often evaluated using small neural-network benchmarks, it remains unclear how experimentally measured ECRAM switching behavior affects pretrained language-model fine-tuning, where update errors can accumulate across many transformer layers.

Here, we develop an ECRAM switching-curve-aware analog fine-tuning framework for pretrained language models. A pretrained EleutherAI Pythia-70M [1] causal language model is fine-tuned on WikiText-2 after converting its linear layers into AIHWKIT [2] analog layers. Measured ECRAM potentiation/depression curves are incorporated into the analog optimizer through a PiecewiseStepDevice model, allowing weight updates to follow the device response. Inspired by Analog Foundation Models [3], we further examine knowledge distillation from a digital teacher, iterative weight clipping, and input/output quantization as stabilization and calibration components.

A pilot sweep over ECRAM curve representations, distillation weights, SI/O quantization settings, and clipping conditions showed that all 48 non-quantized forward-path runs remained stable, whereas uncalibrated SI/O quantized settings produced high-perplexity behavior. Among stable conditions, interpolated ECRAM curves improved perplexity over the original sparse switching curve. In full WikiText-2 fine-tuning, the best condition, using the 5000-state interpolated ECRAM curve with distillation weight 0.2 and no clipping, achieved a perplexity of 75.79.

These results show that measured ECRAM update behavior can be integrated into analog-aware language-model fine-tuning, while clarifying the need for device-specific SI/O calibration. The framework can be extended to larger pretrained models, such as Pythia-160M and Pythia-410M, toward robust in-situ fine-tuning on ECRAM-based analog synaptic arrays.

Electrochemical random-access memory (ECRAM) offers linear, symmetric, low-energy conductance modulation for analog in-memory computing, yet planar ECRAM density (~10 F²) and channel-length-limited switching remain barriers to scalable neuromorphic hardware. Vertically stacked ECRAM (VECRAM) addresses both: verticalization reduces the unit-device footprint to 4 F², and stacking N levels on a shared gate pillar further lowers it to 4 F²/N, while the short vertical channel accelerates ionic switching. Realizing this requires a channel process that is simultaneously conformal on high-aspect-ratio sidewalls and tunable in oxygen-vacancy (V₀) content — mandating an all-atomic-layer-deposition (ALD) active stack. However, ALD growth is intrinsically near-stoichiometric, which suppresses the analog programmability that stacking is meant to exploit.

We resolve this with an in-situ atomic layer reduction (ALR) process for PEALD TiO₂₋ₓ channels: a brief Ar-plasma reduction step (0–45 s) inserted after each oxidation half-cycle within an (ABC)ₘ supercycle, decoupling oxidation and reduction while preserving self-limiting growth. XPS shows the Ti³⁺/V₀ fraction rising monotonically with plasma exposure, and GIXRD/HR-TEM reveal a concurrent amorphous-to-nanocrystalline transition with local anatase A(101) order. Electrochemical impedance spectroscopy (EIS) confirms that the oxygen-ion migration barrier is minimized at Ar plasma 30 s exposure and re-increases with further Ar plasma exposure time.

This V₀ tuning directly controls synaptic behavior: first-pulse conductance overshoot and update nonlinearity (NL) are both minimized at the optimal ALR condition (NL reduced from ~0.45 to ~0.13), tracking the channel activation energy. In device-in-the-loop MNIST simulation, the measured pulse response improves the error rate from 37.6 % (near-stoichiometric) to 10.5 %, approaching the 3.75 % floating-point limit. Building on this channel, we demonstrate an all-ALD N = 2 stacked VECRAM primitive with conformal sidewall coverage, establishing in-situ oxygen-vacancy engineering as a route to combine analog linearity with the density of vertical stacking.

High-performance computing consumes enormous amounts of energy as AI and machine learning become more widespread. Therefore, there is a strong demand for technologies that can improve both computational performance and energy efficiency. Compute-in-memory (CIM) is a promising approach for reducing energy consumption by performing computation directly within memory. In this presentation, we introduce our previous work on CIM and discuss its relationship to inference and generation in machine learning. In our previous report, we showed that in-memory computing using 3D flash memory can be achieved with extremely low power consumption. Since the high input voltage, Vpp, for the word line (WL) driver circuit is externally supplied, both Vread, the WL voltage for unselected cells, and Vcc, the supply voltage for circuits other than the WL driver, can be reduced. As a result, the power consumption during read operation of single-level cells (SLCs) is reduced by 56% at Vcc and by 98% at Vpp. This significant reduction in memory access energy makes it possible to increase the number of activation blocks and WLs used for in-memory computing. We also propose a novel approximate search method that combines sequential multi-block activation with a current control cell (CC cell). Key vector data are stored across multiple blocks, while query vector data are applied as WL voltages, and the on-current of each bit line (BL) is determined by the CC cell. This method requires no additional WL control circuit and uses only one cell per data unit. We demonstrate that the inner product (IP) between key and query vector data can be determined with sufficient accuracy not only for 8-dimensional vectors but also for 128-dimensional vectors. As a result, energy consumption is reduced by 99.4%, and memory access energy reaches as low as 0.17 pJ/bit. This technology is fully compatible with conventional 3D flash memory and is essential for realizing energy-efficient in-memory computing.

 The rapid growth of artificial intelligence (AI) workloads has intensified the need for computing hardware with greater energy efficiency. Analog in-memory computing has emerged as a promising approach, using cross-point arrays of resistive memory devices to store neural network weights as conductance states and perform vector-matrix multiplication directly where data are stored.

 This talk presents electrochemical random-access memory (ECRAM) as a device platform for energy-efficient analog AI accelerators. ECRAM enables gradual and reversible conductance modulation through ion-driven electrochemical switching, providing high programmability, excellent endurance, and low device variability. To understand its switching mechanism at the material level, multi-terminal tungsten oxide-based ECRAM devices are investigated using variable-temperature Parallel Dipole Line (PDL) Hall measurements, which correlate conductance modulation with changes in electronic transport properties.

 At the array level, this talk discusses how ECRAM device nonidealities, such as conductance relaxation and weight-update imbalance, affect neural network training. A hardware-aware training strategy is introduced to compensate for these effects by tuning the programming conditions, improving the robustness of ECRAM-based analog AI hardware.

 Finally, chip-level implementation is demonstrated using a 64×64 ECRAM cross-point array integrated with peripheral circuits for in-situ neural network training. By combining device-level analysis, array-level optimization, and circuit-integrated hardware demonstration, this work shows a pathway toward practical analog training systems based on ECRAM. Overall, this talk highlights the potential of ECRAM as a key building block for energy-efficient analog AI accelerators.

The realization of fault-tolerant quantum computers containing millions of physical qubits requires a paradigm shift in quantum control electronics. Conventional room-temperature architectures suffer from severe wiring complexity, latency, thermal leakage, and energy consumption, while cryogenic CMOS alone faces increasing challenges in scalability and adaptive optimization. Emerging memristive devices offer an attractive alternative by combining non-volatile memory, analog programmability, and in-memory computing within an ultra-compact footprint, enabling local intelligence close to quantum processors [1–3].

In this invited presentation, we summarize our recent progress toward cryogenic memristive computing for scalable quantum information processing. We first present a forming-free Pd/HfO₂ memristor technology that achieves multi-level analog conductance modulation, excellent device uniformity, and femtojoule-level programming energy, providing an efficient hardware platform for neuromorphic and in-memory computing applications [1,2]. Building upon these devices, we demonstrate hardware-accelerated quantum state tomography using memristor-assisted neural-network inference, significantly reducing computational complexity while maintaining high reconstruction accuracy [3]. Furthermore, we discuss a cryogenic computing architecture in which memristive arrays cooperate with cryogenic electronics to perform local bias storage, adaptive calibration, parameter optimization, and distributed information processing near superconducting qubits. Such a distributed architecture has the potential to alleviate wiring bottlenecks, reduce thermal load, and improve system scalability for future quantum computing systems [4,5].

Finally, we discuss future research directions toward integrating cryogenic memristors, neuromorphic computing, and quantum-classical co-design for quantum error correction, distributed quantum control, and intelligent cryogenic hardware. We believe that combining emerging nanoelectronic devices with hardware-efficient computing architectures will provide a promising pathway toward scalable and energy-efficient quantum information systems [6,7].

The ability to generate spike trains is a defining feature of neuronal systems and a key requirement for neuromorphic hardware. In most neuron models and hardware realizations, repetitive firing is achieved through dedicated reset operations [1] or through nonlinear mechanisms that periodically drive the system back to a resting state [2]. This has led to the widespread assumption that some form of reset process is an essential ingredient for integrate-and-fire dynamics.

In this work, we challenge this view by demonstrating that regular spike generation can arise in a simple memristive circuit whose dynamics remain continuous at all times [3]. The proposed architecture combines a passive RC network with a threshold-responsive memory element [4] and is driven by periodic excitation pulses. Despite the absence of reset rules, oscillatory instabilities, or negative differential resistance, the system exhibits robust sequences of well-defined spikes.

The origin of this behavior is traced to a dynamical mismatch between the evolution of the circuit voltage and the adaptation of the internal memory state. Under suitable operating conditions, this mismatch creates recurrent episodes of charge accumulation and rapid release, producing a firing pattern that closely resembles the functionality of integrate-and-fire neurons.

Our results indicate that the transition from quiescent to spiking behavior cannot be predicted solely from static device characteristics. Instead, the response emerges from the interaction between device kinetics and external stimulation. This observation suggests that materials previously regarded as unsuitable for neuromorphic neurons may become viable when operated within the appropriate dynamical regime.

Memristive devices have emerged as promising candidates for next-generation computing systems, offering opportunities to overcome the limitations of conventional von Neumann architectures through low-power operation, analog information processing, and inherent memory functionalities. Among the various material platforms investigated, solution-processed metal oxide memristors out due to their compatibility with low-cost fabrication, scalability, and environmentally conscious manufacturing approaches.

This talk will present recent advances in solution-based memristive technologies, focusing on amorphous metal oxides such as zinc oxide (ZnO), zinc–tin oxide (ZTO), indium gallium zinc oxide (IGZO), aluminum oxide (AlO_x), and molybdenum oxide (MoO_x) and 2D materials. The influence of precursor chemistry, processing parameters, and device engineering on resistive switching performance will be discussed, highlighting strategies to achieve improved stability, reproducibility, and tunable electrical characteristics.

Recent developments in sustainable and printed memristors will be showcased, demonstrating their potential for flexible and eco-designed electronic systems. Beyond memory applications, the talk will explore the implementation of solution-processed memristors in neuromorphic computing, including synaptic functionalities, short-term plasticity, multilevel conductance states, and physical reservoir computing. These results underline the potential of solution-derived memristive devices as energy-efficient hardware platforms for edge artificial intelligence, and distributed sensing systems.

Finally, perspectives on the integration of sustainable materials, printed electronics, and neuromorphic architectures will be discussed, outlining future directions toward scalable, low-cost, and environmentally friendly computing technologies.

Analog Compute-in-Memory (ACiM) is an emerging computing paradigm that improves energy efficiency by performing computation directly within memory arrays, thereby reducing the costly movement of data between memory and processing units. Through highly parallel analog operations, ACiM offers the potential for low-power, high-throughput artificial intelligence computing.

Despite these advantages, practical ACiM systems face significant challenges arising from device variability, noise, limited precision, and nonideal weight-update characteristics. These imperfections can degrade inference accuracy and make efficient on-chip training particularly difficult. Requiring a single synaptic device to simultaneously satisfy the distinct demands of training and inference may also impose overly stringent device specifications.

To relax these requirements, we propose an ACiM memory hierarchy composed of two complementary synaptic-device technologies: one optimized for inference and the other for training. Efficiently integrating these devices requires close device–algorithm co-optimization. We explore three complementary strategies: (1) identifying existing algorithms that are inherently tolerant to device imperfections, (2) adapting conventional algorithms to better exploit the characteristics of analog hardware, and (3) developing new algorithmic frameworks that are intrinsically aligned with device physics.

These studies demonstrate that a heterogeneous memory hierarchy can provide a practical pathway toward efficient and scalable ACiM systems. More broadly, they highlight that tightly coupling device design with algorithm development—rather than optimizing either in isolation—is essential for fully realizing the potential of analog memory-based AI computing.

The semiconductor industry is experiencing an accelerated transformation to overcome the scaling limits of the transistor and to adapt to new requirements in terms of data storage and computation, especially driven by artificial intelligence applications and the internet of things. Within this process, new materials, devices, integration strategies, and system architectures are being developed and optimized. Among them, memristive devices and circuits offer a potential approach to create more compact, energy efficient or better performing systems. In the first part of this talk, I will present our work on novel-materials integration on silicon CMOS microchips for memristive applications [1-2], and I will show you the new testing vehicles that we are offering to the community (for free) to analyse memristive systems. And in the second part, I will discuss how to overcome the main problems of memristive hardware for artificial intelligence, and I will present the Neuro-Synaptic Random Access Memory (NSRAM); this is a 2-transistor cell that exhibits adjustable neural and synaptic response with a yield of 100% and an ultra-low device-to-device variability, and it represents a short-term solution for the implementation of efficient artificial neural networks [3].

*Figure 1 | Inversion-channel MOSFET versus Punch-through MOSFET. a, Schematic of the working principle of a standard transistor switching by forming a channel of minority carriers when the bulk terminal is grounded. b, Transfer characteristic of the transistor. c, Bulk and gate current versus drain voltage for different gate voltages. The current produced by impact ionization, which is driven to ground through the bulk terminal, can be observed. d, Schematic of the working principle of a punch-through transistor switching by impact ionization and accumulation of charges at the bulk terminal, which is kept at a high resistance through a second transistor. e, Drain-to-source current versus drain-to-source voltage exhibiting nonlinear transition and hysteresis. f, Leaky integrate-and-fire time depending on the voltage, duration and frequency of the spikes applied to the drain terminal, and also to the gate voltage applied to the gates of both transistors. Reproduced from reference 17, Copyright Springer-Nature, 2025.

Understanding the electrical mechanisms underlying artificial synaptic plasticity is essential for neuromorphic engineering. This work presents a unified electrical perspective connecting the simple bioelectrochemical dendrites and the greater complexity of memristors as complementary platforms for studying memory effects in artificial brain-inspired synapses. First, we show how conducting polymer dendrites exhibit fractional-order transient responses arising from coupled ionic and electrochemical processes, reproducing key features of synaptic plasticity such as history-dependent dynamics and synaptic learning behavior during morphogenesis [1,2]. Similar electrical signatures are observed in halide perovskite memristors, where ion migration and charge accumulation govern conductance modulation and short-/long-term potentiation [3,4]. By combining Impedance Spectroscopy and transient analysis, we explain the electrical tools for quantifying the physics-based memory effects across biology and neuromorphic engineering. This electrical approach bridges bioelectrochemistry and neuromorphic hardware, offering new insights into the physical origins of synaptic functionality while providing practical guidance for the design and interpretation of next-generation brain-inspired electronic systems.

TBC

Neuromorphic computing has been widely explored to overcome the energy and latency limits of von Neumann architectures. Memristor-based crossbar arrays enable in-memory computing, but their deployment remains limited by stochastic switching, device variability, and poor stability of analog weights. Here, we explore an alternative hardware direction that preserves parallel analog computation while eliminating device-level stochasticity through deterministic weight representations. This enables reliable and scalable inference without relying on fragile analog state control. We emphasize that materials and integration, rather than individual devices, define ultimate performance limits. In this context, three-dimensional integration (M3D) provides a critical pathway by vertically coupling sensing, memory, and computing layers, minimizing data movement and enabling parallel processing. Our prior demonstrations of stackable neuromorphic systems and monolithic 3D integration highlight improvements in bandwidth, latency, and energy efficiency. Finally, we extend this framework toward ultralow-energy operation using strain-engineered devices, where dynamic material modulation enables attojoule-scale switching. This combined strategy—deterministic weight architectures, M3D integration, and new switching mechanisms—offers a scalable path toward next-generation unconventional computing approaching fundamental energy limit.

The realization of brain-inspired based on emerging memory and logic devices requires not only interdisciplinary collaboration but also a coordinated approach spanning materials, devices, circuits, and systems. This presentation highlights recent work on physics-based compact modeling, specifically targeting ferroelectric and CMOS technologies. Traditionally, comphysical phenomena, materials, and devicespact models used in circuit and system design have relied on abstractions that often disregard the underlying physics and the specific dynamics of individual logic and memory devices. However, the design of both future conventional, scaled circuits and unconventional computing primitives necessitates a rigorous understanding of these physical and material dynamics.

Distinct from purely phenomenological approaches, dynamic, physics-based compact models offer strong physical interpretability. This transparency is essential for Design-Technology Co-Optimization (DTCO), as it enables researchers to correlate microscopic physical parameters with macroscopic circuit metrics and TCAD simulations. By providing a reliable and interpretable simulation foundation, these models facilitate the systematic exploration of robust and energy-efficient computing architectures, bridging the gap between emerging devices and mature CMOS integration. This approach allows circuit designers to utilize accurate device models for precise design feedback to technologists, while enabling technologists to interpret electrical characteristics and rigorously relate them to physical degradation models.

In this work, I introduce Heracles [1], a physics-based compact model for HfO2 ferroelectric capacitors and field-effect transistors. Heracles implements this approach by describing the intricate dynamics of HfO2 ferroelectrics, particularly polarization switching and capacitance hysteresis [2], through the explicit modeling of the interaction between polarization switching and charge trapping processes [3]. I will demonstrate several use cases for this model, including retention and imprint analysis, neuromorphic circuit design [4], and circuit-level reliability investigations [5]. Finally, I will discuss how this physics-based methodology extends to logic technologies. Specifically, I will present ongoing work extending the PSP [6] compact model to incorporate reliability effects such as bias-temperature instability (BTI) and charge trapping [7], demonstrating how dynamic, physics-based models enable reliable designs that can account for, or even actively utilize, transient device effects.

Memristive devices are promising candidates for next‑generation non‑volatile memory and synapse modeling in neuromorphic systems due to their simple structure, scalability, and low power operation [1]. Among various material systems, hybrid structures combining electrochemical metallization (ECM) and valence change memory (VCM) mechanisms offer enhanced control over resistive switching (RS) [2]. In this work, we present Ag/Cu‑Ag/a‑Si/ZrO₂:Y₂O₃/p⁺⁺‑Si memristors synthesized by magnetron sputtering, where a thin (6 nm) yttria‑stabilized zirconia barrier layer is inserted between amorphous Si and the p⁺⁺‑Si substrate.

At the initial stage, we also fabricated barrier layers of magnetron SiO_x (Si deposited in DC mode in oxygen), but ZrO₂:Y₂O₃ demonstrated superior reproducibility and stability, so further studies focused on this material [3]. The a‑Si layer (≈5 nm) acts as a host for cations Ag⁺/Cu⁺ diffusion, which provides the formation of alloy nanochannels that determine the switching positions in zirconium oxide. Under bias, Ag⁺/Cu⁺ ions migrate through a‑Si and create metallic nanochannels, whereas oxygen vacancies in ZrO₂:Y₂O₃ form the filaments, yielding a hybrid ECM–VCM switching mechanism.

The devices exhibit multilevel resistive switching with set voltages U_set=2.9 ± 0.3 V and low compliance currents I_cc = 0.2–0.5 mA (Fig. 1). The ON/OFF resistance ratio reaches R_off/R_on ≈ 900 ± 150, and the device‑to‑device dispersion D2D < 16% across three fabrication batches. High‑resistance ON states (~50 kΩ) are particularly important for energy‑efficient 1T1R memory arrays.

These results demonstrate that a‑Si/ZrO₂:Y₂O₃ heterostructures combine reliable current limiting, controlled ion migration, and high batch‑to‑batch reproducibility, making them suitable for transistor‑controlled 1T1R memory at megabit scales and for neuromorphic applications. Future work will focus on BEOL integration and fabrication of crossbar arrays.

The work was financially supported by the Russian Science Foundation grant No. 25-19-90201.

Silicon-on-insulator (SOI) thin layers offer a variety of mechanisms leading to high reconfigurable non-linear expressivity [1, 2], a functionality required for the physical implementation of novel networks, such as Kolmogorow-Arnold networks, and brain inspired computation. Physical neural networks (PNNs) traditionally aim to emulate the architecture of Multilayer Perceptrons (MLPs), where training is confined to linear weights and hardware nonlinearities are treated as fixed constraints. We recently reported on a paradigm shift by implementing Physical Kolmogorov-Arnold Networks (KANs) on Silicon-on-Insulator (SOI) technology [F. Taglietti, A. Pulici, M. Roxburgh, G. Seguini, I. Vidamour, S. Menzel, E. Franco, M. Laus, Eleni Vasilaki, M. Perego, T. J. Hayward, M. Fanciulli, J. C. Gartside, “Learning Nonlinear Heterogeneity in Physical Kolmogorov-Arnold Networks” https://arxiv.org/abs/2601.15340]. Unlike MLPs, KANs place learnable nonlinear functions directly on the edges of the network. We experimentally demonstrated this with Synaptic Nonlinear Elements (SYNEs), novel microscale SOI devices that exhibit highly reconfigurable nonlinear I-V characteristics. The intricate physics, rooted in non-equilibrium carrier transport and complex electrostatic interactions within the multi-gate SOI structure, generate rich nonlinearities including negative differential resistance (NDR) and multi-stable states. Crucially, the SYNE's configuration is augmented by a floating back-gate effect, wherein charge trapping within the dielectric layer modulates the local potential, possibly enabling long-term plasticity and persistent storage of the learned "function shape" rather than just a linear weight. To support our understanding of the device operation, we have performed 3D simulations using Synopsys Sentaurus TCAD. In the model we have included the SOI layer, the buried oxide and a portion of the doped Si substrate. Interface states at the Si/SiO₂ interfaces, revealed by electrically detected magnetic resonance (EDMR), with a Gaussian energy distribution have been considered to model presence of P_b0 centers. The simulated device characteristics qualitatively reproduce the experimental data, revealing the critical role of the floating back gate and of the interface defects, exploited to achieve the required non-linear expressivity. By leveraging the inherent "nonlinear heterogeneity" of SOI devices, we have shown that the variability of physical substrates can be a computational asset rather than a limitation. Our physical KANs operate at room temperature with microampere currents and 2 MHz speeds, consuming approximately 750 fJ per nonlinear operation. We validate this architecture across diverse tasks: i.e., nonlinear binary classification tasks and the prediction of Li-ion battery dynamics from noisy sensor data. Our results demonstrate that Physical KANs outperform equivalently-parameterized software MLPs and require up to two orders of magnitude fewer devices than conventional linear weight-based physical networks. This work establishes learned physical nonlinearity as a hardware-native computational primitive for efficient, compact, and high-performance neuromorphic SOI systems. We construct KAN synapses by summing the outputs of multiple SYNE devices in parallel. This creates a highly expressive, learnable edge that replaces the standard "weight \times input" operation. The hardware achieved 99.0% accuracy on the Yin-Yang classification task. Notably, the Physical KAN reached target accuracy with 100x fewer physical parameters than a standard linear PNN. This research demonstrates that the future of SOI-based neuromorphic hardware lies in embracing and training natural nonlinear complexities. Physical KANs provide a mathematically grounded framework to exploit these complexities, leading to AI hardware that is significantly more resource-efficient than current digital or analog-linear counterparts. SYNEs offers also the possibility to realize novel brain inspired devices, and this aspect will be also discussed.

Artificial neural network (ANN)-based computing can provide excellent learning, classification, and inference characteristics that are close to, and in some cases beyond, those found in natural intelligence (i.e., the human brain), whereas the enormous amounts of power required by ANN are far higher than that required by human beings. To overcome the low energy efficiency of ANN computing, physical reservoir computing (PRC) is particularly attractive because it can significantly reduce the computational resources required to process time-series data by leveraging the nonlinear responses of a ‘reservoir’ (a material or device acting as a dynamical system) to input signals. Recently, we have developed high-performance PRC devices based on iontronic phenomena. One example is an ion-gating reservoir (IGR), which utilizes ion-electron coupled dynamics in the vicinity of a solid electric double layer at the diamond/Li+ solid electrolyte interface [1]. The edge-of-chaos state of the IGR enabled the best computational capacity. Furthermore, the IGR, consisting of graphene and ion-gel, demonstrates an exceptionally broad responsive range, from 1 MHz to 20 Hz, while maintaining a high information processing capacity and adaptability across multiple time scales [2]. The IGR achieved deep learning (DL)-level accuracy in chaotic time series prediction tasks while reducing computational resource requirements to 1/100 of those needed by DL. Another example is a magnonic PRC device that utilizes the high-speed nonlinear dynamics of interfered spin waves in a ferrimagnetic Y3Fe5O12 single crystal [3].

The high PRC performance of the IGR is particularly advantageous for application to in-sensor computing, which is a system-level paradigm in which the sensor element itself not only converts an external stimulus into an electrical signal but also carries out local data processing (e.g., feature extraction, thresholding, logic, neuromorphic operations) on that signal [4]. One example is a real-time spoken-digit recognition system that directly processes throat vibrations by integrating a π–gel-electret mechano-electric generator (MEG) sensor with a multi-channel ion-gel/graphene IGR [5]. This hybrid MEG–IGR system achieves an impressive real-time spoken-digit recognition accuracy of 96.8%, demonstrating that IGR can efficiently extract discriminative spatiotemporal features from raw biomechanical signals. Another example is a high-speed gas classification with a membrane-type surface stress sensor. The IGR, with its broad responsive range and small volume, can serve as a versatile platform for high-performance in-sensor computing with various sensors.

Inspired by memristive concepts, magneto-ionics offers a powerful route to control magnetic properties via ionic motion, particularly at ferromagnet/oxide interfaces. This capability creates new opportunities for spintronic devices with reconfigurable, multistate, and cumulative gating functionalities, while also providing a promising platform for neuromorphic hardware that combines non-volatile binary magnetic states with the analogue tunability of ionic systems.

I will discuss strategies for implementing synaptic functionalities through magneto-ionic control of magnetic anisotropy in CoFeB-based devices. These nanodevices can encode multiple non-volatile, electrically readable states and support advanced bioinspired behavior. In particular, we show that synaptic potentiation and depression can be tuned by an applied magnetic field, enabling dynamic control over the linearity of weight updates. This effect resembles neuromodulation in biological systems, and neural network simulations indicate that improved update linearity enhances learning accuracy across a broad range of learning rates.

I will also present approaches based on volatile ionic effects in spintronic devices. Here, gate-induced transient changes in magnetic anisotropy are used to control the switching probability of a spin-orbit-torque-driven magnetic memory element. While the magnetic state remains binary and non-volatile, the magneto-ionic gating state is volatile, allowing the device to separate long-term information storage from short-term update eligibility. This separation is particularly relevant for reward-based learning schemes and highlights the broader potential of magneto-ionics for neuromorphic spintronics.