Publication date: 21st July 2025
On conventional computers, the performance of AI models is limited by the data transfer between the memory and the processor. Compute-in-Memory architectures offer a new paradigm: Vector-Matrix Multiplications may be performed by a voltage drop through a matrix of programmable resistances, the “synaptic weights”. Ferroelectric materials are excellent candidates for their realization:[1] in a two- or three-terminals geometry and in combination with a semiconducting oxide,[2], [3], [4] the conductance is programmed by controlling the configuration of the ferroelectric domains.
The unique fluorite unit cell of HfZrO4 allows for the stabilization of ferroelectricity below 3 nm,[5] facilitating the scaling of synaptic weights. The mechanisms governing the resistive switching in WOx / HZO-SL (5 nm) bilayers are discussed. The effect of the programming pulse duration and amplitude on the polarization switching are investigated, from milliseconds to nanoseconds timescales. Devices of different sizes and shapes are measured down to 500 nm in dimension. For an device size of 1 micrometer square, an On/Off ratio as high as 8 is obtained for 20 ns pulses, a 4-fold improvement compared to 40 um devices.
The relatively low crystallization temperature of polycrystalline hafnium oxide / zirconium oxide superlattices (HZO-SL) is compatible with the Back-End-Of-Line (BEOL) of CMOS transistors.[6], [7] These results not only demonstrate the functionalization of the BEOL with synaptic weights, but also pave the way for the integration of ferroelectric field-effect transistors with Beyond CMOS semiconductors.
[1] T. Mikolajick, et al., “From Ferroelectric Material Optimization to Neuromorphic Devices,” Advanced Materials, 2023, doi: 10.1002/adma.202206042.
[2] L. Bégon-Lours et al., “Scaled, Ferroelectric Memristive Synapse for Back-End-of-Line Integration with Neuromorphic Hardware,” Advanced Electronic Materials, 2022, doi: 10.1002/aelm.202101395.
[3] M. Halter et al., “Back-End, CMOS-Compatible Ferroelectric Field-Effect Transistor for Synaptic Weights,” ACS Appl. Mater. Interfaces, 2020, doi: 10.1021/acsami.0c00877.
[4] M. Halter, et al., “A multi-timescale synaptic weight based on ferroelectric hafnium zirconium oxide,” COMMUNICATIONS MATERIALS, 2023, doi: 10.1038/s43246-023-00342-x.
[5] L. Bégon-Lours et al., “Effect of cycling on ultra-thin HfZrO4, ferroelectric synaptic weights,” Neuromorph. Comput. Eng., 2022, doi: 10.1088/2634-4386/ac5b2d.
[6] L. Bégon-Lours et al., “Back-End-of-Line Integration of Synaptic Weights using HfO2/ZrO2 Nanolaminates,” Advanced Electronic Materials, 2024, doi: 10.1002/aelm.202300649.
[7] R. Hamming-Green, et al., “Multi-Level, Low-Voltage Programming of Ferroelectric HfO 2 /ZrO 2 Nanolaminates Integrated in the Back-End-Of-Line,” in 2024 8th IEEE EDTM, Bangalore, India, 2024, doi: 10.1109/EDTM58488.2024.10511719.
The authors acknowledge the contributions of A. Emboras and M. Luisier to this work. We thank S. R. Mamidala, D. F. Falcone, U. Drechsler, A. Olziersky, and S. Reidt at IBM Research and the BRNC. Research funded by SNSF ROSUBIO #218438, SERI SwissChips, EU Horizon Europe ViTFOX #101194368
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