Receptron Hardware Platform for Real Time Learning and Classification
Paolo Milani a b, Bruno Paroli a b, Francesca Borghi a b, Marco Potenza a b, Stefano Radice a
a University of Milano, via Celoria 16, Milano, Italy
b Gruppo Cibernetici Operativi (GRUCIO)
Proceedings of MATSUS Spring 2026 Conference (MATSUSSpring26)
H4 Neuromorphic devices and systems
Barcelona, Spain, 2026 March 23rd - 27th
Organizer: Francesca Borghi
Invited Speaker, Paolo Milani, presentation 341
Publication date: 15th December 2025

Tiny processing entities, such as microcontrollers, are at the basis of the Internet of Things paradigm. The integration of Machine Learning models on small computing units require the development of architectures and hardware solutions that do not need the processing support from the cloud and the training processes typical of Artificial Intelligence, which are power consuming and involves data security and privacy risks [1]. To face this challenge, a novel threshold logic gate design, called Receptron, has been recently proposed as an alternative to multilayer architectures based on perceptrons typical of artificial neural networks [2]. The receptron is based on the use of nonlinear weights thus widening the spectrum of Boolean computable functions while simplifying training thanks to a random search protocol [3,4]. The hardware implementation of the Receptron model has been demonstrated to rurn on standard microcontrollers and CMOS components.

The reconfigurability and functional completeness of the receptron allows faster, more efficient and possibly edge, data processing compared to traditional architectures used for artificial neural networks. Here we report the fabrication of a receptron-based electronic board for edge data processing and classification working on analog inputs and capable to learn with an extremely reduced training.

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