Leveraging Mature Superconducting Materials for Scalable Quantum Analog Hardware
Paloma Machain a
a Qilimanjaro Quantum Tech
Proceedings of MATSUS Spring 2026 Conference (MATSUSSpring26)
H1 Quantum and Probabilistic Computation
Barcelona, Spain, 2026 March 23rd - 27th
Organizers: Pol Forn-Díaz and Jiyong Woo
Invited Speaker, Paloma Machain, presentation 790
Publication date: 15th December 2025

The development of qubits has largely been guided by the requirements of fault-tolerant, gate-based quantum computing and, more recently, by topological quantum computing paradigms. These approaches impose exceptionally stringent constraints on materials quality, coherence times, and device uniformity, often requiring complex materials stacks, bespoke fabrication processes, and long technology maturation cycles. In contrast, quantum analog computing operates in a distinct regime in which scalability, reproducibility, and integration density take precedence over ultra-high coherence, enabling alternative materials and fabrication strategies.

This invited talk presents a materials-centric perspective on the realization of superconducting qubits for quantum analog computing, emphasizing the advantages of leveraging mature superconducting materials systems and CMOS-compatible microfabrication technologies. The use of well-established thin-film superconductors, conventional Josephson junction processes, and industrial process control enables high fabrication yield, improved parameter uniformity, and vertical integration across the hardware stack. These characteristics are essential for scaling quantum analog processors to large qubit counts while maintaining manageable complexity, cost, and development timelines.

Key materials challenges defining the performance envelope of quantum analog hardware will be discussed, including superconducting film uniformity, interface and dielectric losses, junction reproducibility, wiring density, and three-dimensional integration constraints. These challenges are contrasted with those encountered in fault-tolerant digital and topological quantum computing, illustrating how differing system-level requirements lead to fundamentally different materials bottlenecks and fabrication trade-offs. Rather than treating these paradigms as competing approaches, this perspective frames them as complementary stages within a broader superconducting quantum technology roadmap.

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