The Ouroboros of Memristors: Neural Networks Facilitating Memristor Programming
Zhenming Yu a b, Ming-Jay Yang a, Jan Finkbeiner a b, Sebastian Siegel a, John Paul Strachan a b, Emre Neftci a b
a Forschungszentrum Jülich, Germany
b RWTH Aachen University, Faculty of Electrical Engineering and Information Technology, Aachen, Germany
Proceedings of Neuronics Conference (Neuronics)
València, Spain, 2024 February 21st - 23rd
Organizers: Sabina Spiga and Juan Bisquert
Oral, Zhenming Yu, presentation 010
Publication date: 18th December 2023

Memristive devices hold promise to improve the scale and efficiency of machine learning and neuromorphic hardware, thanks to their compact size, low power consumption, and the ability to perform matrix multiplications in constant time. However, on-chip training with memristor arrays still faces challenges, including device-to-device and cycle-to-cycle variations, switching non-linearity, and especially SET and RESET asymmetry [1], [2].

To combat device non-linearity and asymmetry, we propose to program memristors by harnessing neural networks that map desired conductance updates to the required pulse times. With our method, approximately 95% of devices can be programmed within a relative percentage difference of ±50% from the target conductance after just one attempt. Moreover, our neural pulse predictor demonstrates a significant reduction in memristor programming delay compared to traditional write-and-verify methods, particularly advantageous in applications such as on-chip training and fine-tuning.

Upon deployment, the neural pulse predictor can be integrated into memristor accelerators, predicting pulses with an O(1) time complexity while utilizing a minimal fraction of the available memristor arrays, reducing hardware overhead compared with previous works [3]-[6]. Additionally, multiple networks can be trained to operate in parallel and enhance precision across various conductance ranges.

Our work contributes significantly to the practical application of memristors, particularly in reducing delays in memristor programming. This work also offers a fresh perspective on the symbiotic relationship between memristors and neural networks and sets the stage for innovation in memristor optimizations.

This work was sponsored by the Federal Ministry of Education, Germany (project NEUROTEC-II grant no. 16ME0398K and 16ME0399). We thank Dr. Vasileios Ntinas for his help with the simplified model and Dr. Stephan Menzel for his advice on the JART model noise implementations.

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