Equivalent Circuit Representation of Hysteresis in Solar Cells Caused by Interface Charge Accumulation
Kazuhiko Seki a
a AIST, Tsukuba, Ibaraki 305-8565, Japan
Asia-Pacific International Conference on Perovskite, Organic Photovoltaics and Optoelectronics
Proceedings of International Conference Asia-Pacific Hybrid and Organic Photovoltaics (AP-HOPV17)
Yokohama-shi, Japan, 2017 February 2nd - 4th
Organizers: Tsutomu Miyasaka and Iván Mora-Seró
Poster, Kazuhiko Seki, 088
Publication date: 7th November 2016

We theoretically study hysteresis in the current-voltage characteristics caused by the transient response of the electric field from the accumulated charges. We derived an equivalent circuit from the mechanism of charge carriers accumulation in the charge transport layer of a solar cell. By solving the equivalent circuit model, we show some of the features of hysteresis in perovskite solar cells.

Recently, to reduce or even to eliminate this hysteresis, the TiO2 electron transport layer was replaced with another layer.  The results presented here are consistent with the reduced hysteresis that was obtained by introducing these structures, because the charges would accumulate at the interface between the charge generation layer and the electron transport layer.

While our results are qualitative, they do clearly reproduce the basic hysteresis features, such as a higher current when scanned from the open circuit (OC) side as compared with that obtained when scanned from the short circuit (SC) side, and the large hysteresis at the OC side when compared with that on the SC side for the planar structured cells.

K. Seki, Appl. Phys. Lett. 109, 033905 (2016).


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