The realization of brain-inspired based on emerging memory and logic devices requires not only interdisciplinary collaboration but also a coordinated approach spanning materials, devices, circuits, and systems. This presentation highlights recent work on physics-based compact modeling, specifically targeting ferroelectric and CMOS technologies. Traditionally, comphysical phenomena, materials, and devicespact models used in circuit and system design have relied on abstractions that often disregard the underlying physics and the specific dynamics of individual logic and memory devices. However, the design of both future conventional, scaled circuits and unconventional computing primitives necessitates a rigorous understanding of these physical and material dynamics.

Distinct from purely phenomenological approaches, dynamic, physics-based compact models offer strong physical interpretability. This transparency is essential for Design-Technology Co-Optimization (DTCO), as it enables researchers to correlate microscopic physical parameters with macroscopic circuit metrics and TCAD simulations. By providing a reliable and interpretable simulation foundation, these models facilitate the systematic exploration of robust and energy-efficient computing architectures, bridging the gap between emerging devices and mature CMOS integration. This approach allows circuit designers to utilize accurate device models for precise design feedback to technologists, while enabling technologists to interpret electrical characteristics and rigorously relate them to physical degradation models.

In this work, I introduce Heracles [1], a physics-based compact model for HfO2 ferroelectric capacitors and field-effect transistors. Heracles implements this approach by describing the intricate dynamics of HfO2 ferroelectrics, particularly polarization switching and capacitance hysteresis [2], through the explicit modeling of the interaction between polarization switching and charge trapping processes [3]. I will demonstrate several use cases for this model, including retention and imprint analysis, neuromorphic circuit design [4], and circuit-level reliability investigations [5]. Finally, I will discuss how this physics-based methodology extends to logic technologies. Specifically, I will present ongoing work extending the PSP [6] compact model to incorporate reliability effects such as bias-temperature instability (BTI) and charge trapping [7], demonstrating how dynamic, physics-based models enable reliable designs that can account for, or even actively utilize, transient device effects.