Publication date: 24th July 2026
The semiconductor industry is experiencing an accelerated transformation to overcome the scaling limits of the transistor and to adapt to new requirements in terms of data storage and computation, especially driven by artificial intelligence applications and the internet of things. Within this process, new materials, devices, integration strategies, and system architectures are being developed and optimized. Among them, memristive devices and circuits offer a potential approach to create more compact, energy efficient or better performing systems. In the first part of this talk, I will present our work on novel-materials integration on silicon CMOS microchips for memristive applications [1-2], and I will show you the new testing vehicles that we are offering to the community (for free) to analyse memristive systems. And in the second part, I will discuss how to overcome the main problems of memristive hardware for artificial intelligence, and I will present the Neuro-Synaptic Random Access Memory (NSRAM); this is a 2-transistor cell that exhibits adjustable neural and synaptic response with a yield of 100% and an ultra-low device-to-device variability, and it represents a short-term solution for the implementation of efficient artificial neural networks [3].
*Figure 1 | Inversion-channel MOSFET versus Punch-through MOSFET. a, Schematic of the working principle of a standard transistor switching by forming a channel of minority carriers when the bulk terminal is grounded. b, Transfer characteristic of the transistor. c, Bulk and gate current versus drain voltage for different gate voltages. The current produced by impact ionization, which is driven to ground through the bulk terminal, can be observed. d, Schematic of the working principle of a punch-through transistor switching by impact ionization and accumulation of charges at the bulk terminal, which is kept at a high resistance through a second transistor. e, Drain-to-source current versus drain-to-source voltage exhibiting nonlinear transition and hysteresis. f, Leaky integrate-and-fire time depending on the voltage, duration and frequency of the spikes applied to the drain terminal, and also to the gate voltage applied to the gates of both transistors. Reproduced from reference 17, Copyright Springer-Nature, 2025.
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