Publication date: 24th July 2026
The realization of fault-tolerant quantum computers containing millions of physical qubits requires a paradigm shift in quantum control electronics. Conventional room-temperature architectures suffer from severe wiring complexity, latency, thermal leakage, and energy consumption, while cryogenic CMOS alone faces increasing challenges in scalability and adaptive optimization. Emerging memristive devices offer an attractive alternative by combining non-volatile memory, analog programmability, and in-memory computing within an ultra-compact footprint, enabling local intelligence close to quantum processors [1–3].
In this invited presentation, we summarize our recent progress toward cryogenic memristive computing for scalable quantum information processing. We first present a forming-free Pd/HfO₂ memristor technology that achieves multi-level analog conductance modulation, excellent device uniformity, and femtojoule-level programming energy, providing an efficient hardware platform for neuromorphic and in-memory computing applications [1,2]. Building upon these devices, we demonstrate hardware-accelerated quantum state tomography using memristor-assisted neural-network inference, significantly reducing computational complexity while maintaining high reconstruction accuracy [3]. Furthermore, we discuss a cryogenic computing architecture in which memristive arrays cooperate with cryogenic electronics to perform local bias storage, adaptive calibration, parameter optimization, and distributed information processing near superconducting qubits. Such a distributed architecture has the potential to alleviate wiring bottlenecks, reduce thermal load, and improve system scalability for future quantum computing systems [4,5].
Finally, we discuss future research directions toward integrating cryogenic memristors, neuromorphic computing, and quantum-classical co-design for quantum error correction, distributed quantum control, and intelligent cryogenic hardware. We believe that combining emerging nanoelectronic devices with hardware-efficient computing architectures will provide a promising pathway toward scalable and energy-efficient quantum information systems [6,7].
The authors acknowledge the support of Delft University of Technology (TU Delft) and QuTech. The authors thank their collaborators for valuable discussions and technical support.
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