Artificial neural networks (ANNs) are composed of nodes (neurons) and edges (synapses), in which the weighted sum of inputs plays a central role in intelligent tasks. Memristors have been the core elements in the physical implementation of multiply-and-accumulate (MAC) operations for ANNs, where they store synaptic weights in either analog (multiple values) or digital (binary values) form. However, such a weight representation may not be the most feasible approach for incorporating such devices into an ANN or deep neural network, especially given that the MAC arrays are prone to various forms of noise even with write-and-verify algorithms and error-tolerant operational methods. Besides, most of the peripheral circuits in the ANN hardware still operate in digital form, so the overhead of converting analog outputs to digital values and digital values to analog inputs is a significant issue. 

This presentation reviews what else can be done with the new memristor functionality. It first classifies the application fields into two categories with edge and node representations. For edge applications, it discusses reservoir computing kernels that enrich input information by projecting the original data into hyperdimensional spaces. More recent forward-forward learning methods, which may eliminate several issues associated with conventional backpropagation, are also introduced. Another interesting field is the application of specialized memristive hardware to NP-hard problems in graphics, such as protein folding, where the underlying physical laws greatly aid in finding optimal solutions. For the node applications, the principles and issues of probabilistic-bit (p-bit) devices are introduced and discussed. In this case, the computationally hard problems are mapped onto the coupler network, and node-state (or spin-state) optimization is performed based on the Ising or Potts Hamiltonian. The general and critical issues in such energy-based optimization include reaching the global minimum, where the noisy responses of the memristive p-bits are helpful. Still, their practical implications, compared with the software solution, require careful evaluation of accuracy, power consumption, and time-to-solution, while accounting for peripheral circuits. The successful implementation of these new hardware requires careful design-technology co-optimization between the algorithm, circuit design, and technology sectors.