Building a Memory Hierarchy for Analog Compute-in-Memory through Device–Algorithm Co-Optimization
Sangbum Kim a b c
a Department of Materials Science and Engineering, Seoul National University, Seoul, Korea.
b Department of Materials Science and Engineering, Research Institute of Advanced Materials (RIAM), Seoul National University, 1 Gwanak-ro, Gwanak-gu, Seoul 151-742, Republic of Korea
c Inter-University Semiconductor Research Center (ISRC), Seoul National University, Seoul, South Korea
Proceedings of Neuronics Conference 2026 (Neuronics26)
Seoul, Korea, Republic of, 2026 September 8th - 10th
Organizers: Valeria Bragaglia and Seyoung Kim
Invited Speaker, Sangbum Kim, presentation 025
Publication date: 24th July 2026

Analog Compute-in-Memory (ACiM) is an emerging computing paradigm that improves energy efficiency by performing computation directly within memory arrays, thereby reducing the costly movement of data between memory and processing units. Through highly parallel analog operations, ACiM offers the potential for low-power, high-throughput artificial intelligence computing.

Despite these advantages, practical ACiM systems face significant challenges arising from device variability, noise, limited precision, and nonideal weight-update characteristics. These imperfections can degrade inference accuracy and make efficient on-chip training particularly difficult. Requiring a single synaptic device to simultaneously satisfy the distinct demands of training and inference may also impose overly stringent device specifications.

To relax these requirements, we propose an ACiM memory hierarchy composed of two complementary synaptic-device technologies: one optimized for inference and the other for training. Efficiently integrating these devices requires close device–algorithm co-optimization. We explore three complementary strategies: (1) identifying existing algorithms that are inherently tolerant to device imperfections, (2) adapting conventional algorithms to better exploit the characteristics of analog hardware, and (3) developing new algorithmic frameworks that are intrinsically aligned with device physics.

These studies demonstrate that a heterogeneous memory hierarchy can provide a practical pathway toward efficient and scalable ACiM systems. More broadly, they highlight that tightly coupling device design with algorithm development—rather than optimizing either in isolation—is essential for fully realizing the potential of analog memory-based AI computing.

This work was supported by K-CHIPS (Korea Collaborative Hightech Initiative for Prospective Semiconductor Research) (2410010063, 20024709, 23040-15FC) funded by the Ministry of Trade, Industry and Energy (MOTIE, Korea), by the National R&D Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT (RS-2025-07402970), and by Samsung Electronics.

© FUNDACIO DE LA COMUNITAT VALENCIANA SCITO
We use our own and third party cookies for analysing and measuring usage of our website to improve our services. If you continue browsing, we consider accepting its use. You can check our Cookies Policy in which you will also find how to configure your web browser for the use of cookies. More info