The potentiation and depression of synaptic conductivity regulate the plasticity and adaptability of synapses. In this discussion, we examine the general dynamic characteristics of ionic or electronic current conduction in memristors, which underpin the fundamental principles of synaptic activity. Key model requirements for memristors or chemical inductors to achieve conductance adaptation in response to incoming stimuli are outlined. We also propose various criteria, such as hysteresis and rectification, to achieve these properties. Additionally, we describe a range of diagnostic methods that link nonlinear time responses, the nonlinear cycling of current-voltage curves, and the linear frequency responses from impedance spectroscopy to evaluate adaptation properties. The frequency domain analysis of memristors and more generally, of conducting systems with memory features of some kind, provides essential information about the dynamic behaviour of the system. The impedance response of a memristor can be represented as a linear circuit made of resistances, capacitors, and inductors, with voltage-dependent elements. The equivalent circuit properties also establish the criteria for a Hopf bifurcation that produces spiking of artificial neurons.

The growing demand for data-driven applications calls for computing architectures going beyond traditional von Neumann architectures, where the separation between memory and processing units causes increasing latency and bandwidth bottlenecks [1]. This challenge has sparked interest in emerging ‘neuromorphic’ devices and systems, where memory and computation are seamlessly co-integrated. The brain-inspired circuits can be built from such devices by combining novel metal-oxide materials, such as HfO2 [2] and VO2 [3] that can implement synaptic and neuronal functions in the neural networks [4]. These neuro-inspired devices exhibit promising features, such as ultrafast and analog resistive switching at low energy costs. In this talk, I will present our work on VO2-based oscillator networks solving combinatorial optimization problems, including Graph Coloring, Max-cut, and Max-3SAT problems [5]. Additionally, the in-memory computing architecture of the system will be introduced by combining with HfO2-based resistive RAM (ReRAM) devices for enhanced performance and efficiency.

A comparison of the resistive switching (RS) operation in memristors based on HfO₂, Al₂O₃ and a bilayer made of both oxides is presented. The devices are fabricated using the TiN/Ti/dielectric/TiN stack, and they are measured for thousands of cycles to assess their cycle-to-cycle variability. A statistical analysis is performed including 1D and 2D algorithms. A compact modeling approach (using a modified version of the Stanford model) is implemented to describe RS operation and variability. Finally, a 3D circuit-breaker-based simulation tool is employed to fit the experimental data and assess the role of thermal effects in the different dielectrics employed.

Bipolar valence change memory devices have been fabricated and measured [1]. The memristors fabrication is based on highly doped N-type (ρ = 4 mΩ·cm) silicon wafers with a 20 nm-thick Ti adhesion layer. The bottom electrode consists of a 50 nm-thick W layer. The dielectrics were grown by atomic layer deposition. The top electrode is composed of a 200 nm TiN/10 nm Ti bilayer. Thousands of I-V curves were measured in both types of devices under the ramped voltage stress regime. Resistive switching was characterized by means of consecutive set and reset cycles. RS parameters, such as the set and reset voltages, were obtained. 

The set and reset voltages are obtained using different algorithms to assess the variability. We calculate one-dimensional coefficients of variation (1DCV) and two-dimensional ones (2DCV), the latter are explained in [2].

We complement the study by means of a compact modeling approach. We are able to reproduce the change that takes place in the I-V curves of the different technologies. Simulation using a 3D circuit breaker tool [3] is also performed to fit average I-V curves for the technologies studied here.

Valence Change Memory (VCM) cells are emerging as promising candidates for non-volatile memory and neuromorphic computing applications [1,2]. These devices typically employ a simple metal-insulator-metal (MIM) structure, where an applied voltage modulates the insulating oxide layer. This modulation drives the incorporation and redistribution of oxygen vacancies, enabling the oxide layer's resistance to switch dynamically between a high-resistance state (HRS) and a low-resistance state (LRS). These resistance states are non-destructively readable, offer rapid switching, and exhibit excellent scalability, CMOS (complementary metal-oxide-semiconductor) compatibility, and low power consumption [3–6]. 

Despite their advantageous properties, the reliability of VCM ReRAM devices remains a critical challenge, particularly as these devices approach commercial viability [7]. Experimental studies, such as those by Kempen et al., have demonstrated that extrinsic doping can significantly enhance the reliability of TaO_x-based ReRAM by improving endurance and lowering the forming voltage [8]. 

Building upon these experimental insights, we incorporated dopants into our three-dimensional Kinetic Monte Carlo (3D KMC) simulation framework previously developed for analysing reliability phenomena in VCMs [9,10]. Our simulations investigated the influence of dopant concentration and energy levels on key reliability metrics, including variability and retention. The results corroborate the experimentally observed improvements, revealing the positive impact of doping on reliability and providing new insights into the underlying physical mechanisms. These findings contribute to advancing the understanding of dopant-driven reliability enhancements in VCM ReRAM technology.

The industry adoption of memristor-based technologies hinges upon improvements in several key performance metrics for these devices, including controllable switching, multiple resistive states, reducing the variability over multiple switching cycles, and reduction in the switching and forming voltages, depending upon the specific requirements for different application domains. Of these, a new kind of memristor comprising two different metal oxides as active layers between inert electrodes, referred to as the bilayer resistive RAM (ReRAM), has been shown to possess gradual analogue switching characteristics [1], making it particularly suitable to act as the variable coupling element between oscillators within the energy-efficient neuromorphic computing framework of oscillatory neural networks (ONNs) [2,3]. However, the atomistic mechanisms underlying the unique behaviour of bilayer ReRAMs remain to be uncovered, which is crucial for understanding and further optimization of this technology for its integration with the ONN computing hardware. Another peculiar characteristic of this device is the high voltage requirement for the forming step, which is the first process when the initial structural changes related to the resistance-switching behavior occur in the pristine device [1]. In this work, we reveal the detailed ionic response in this device to understand its filamentary forming mechanisms and explain its observed characteristics using atomistic simulations. For this, we use an implementation of a novel molecular dynamics simulation framework, integrating the local electrochemical potential formulation (called EChemDID) [4] with the charge transfer ionic potential (CTIP) [5,6], to capture the accurate physics of this device. We clarified the differences in the peculiar responses of each of the anionic and cationic species in the pristine structure in response to applied voltage and joule heating in the device, and the physical reasons underlying these mechanisms. Our results indicate that an oxygen-rich region could form on top of the filament in bilayer ReRAM devices, as a consequence of repulsion of the Tantalum ions that occurs even at lower temperatures. Furthermore, the filament initiates at the cathodic interface of the active MO layers by agglomeration of the vacancies when the applied voltage is beyond a critical threshold voltage, and an increase in temperature significantly accelerates the growth of the filament, particularly owing to an increased thermally excited mobility of tantalum and oxygen ions promoting bond breakage and vacancy formation. These mechanisms reveal the key processes underlying forming in the bilayer ReRAM, which could be controlled for directed optimization and further improvement of the key performance metrics of these novel devices. This project has received funding from the EU’s Horizon program under Projects No. 101092096, PHASTRAC.

Memristor devices post-fabricated on top of CMOS circuits promise the avenue to implement low power neuromorphic cores implementing in-memory computing architectures, where the dense memristive matrix act as dense synaptic adaptive memory following bioinspired learning rules as spike-time-dependent-plasticity (STDP). However, the present CMOS-memristive technologies present integration density limitations due to the need of compound MOS-memristor synapses (called 1T1R) as well as problems with control memristive analog values and its variations.

Circuit design techniques can help to overcome this limitations as well as served as an orientation for technological developments to make possible the implementation of advanced low power CMOS-memristive SNN computing architectures.

At IMSE neuromorphic group, we have implemented a dense CMOS-memristive architecture exploiting a CMOL-like geometry to partially overcome the 1T-1R integration limit. Furthermore, we have developed stochastic binary STDP learning rule and experimentally demonstrate its robust performance on a CMOS-memristive hardware. During this talk, the CMOS-memristive SNN computing hardware will be explained, with experimental characterization results at the device and neural system level.

In recent years, the cloud-based approach to data classification has been challenged by the edge computing paradigm, which has enabled real-time data processing at the network edge, ideally in close proximity to the sensor that is collecting the data. This paradigm presents significant challenges in terms of power efficiency, compactness, and latency [1, 2]. It is therefore necessary to explore unconventional hardware solutions that are able to meet these exacting requirements.

Brain-inspired architectures, particularly spiking neural networks (SNNs), have the potential to achieve low-latency computation and stateful, energy-efficient operations [3]. However, their current implementations are primarily based on digital or mixed-signal Complementary Metal-Oxide-Semiconductor (CMOS) technologies, which present significant challenges in meeting the demanding memory, area, and power constraints of computing at the network edge. [1].

The integration of emerging memory technologies in the back end of the line (BEOL) of CMOS circuits holds significant promise for enhancing the capabilities of CMOS technology [2, 4] for the development of neuromorphic hardware [5]. The exploitation of their unique properties – including operation voltages compatible with current CMOS technology, as well as analogue, neural-/synaptic-like behaviour – offers an attractive opportunity for realizing energy-efficient and massively parallel computing architectures in conjunction with CMOS technology [3, 5]. Indeed, these features enable efficient computation, neural dynamics, and synaptic plasticity, which are essential traits for emulating the brain's functionality in hardware [4, 6]. However, the achievement of this goal is still an open challenge at several levels, from the fabrication to the integration with circuits to the architecture.

This talk emphasizes the necessity of design-technology co-optimization (DTCO) of emerging memory devices and CMOS circuits to facilitate seamless integration and to leverage the strengths of both technologies. Additionally, it discusses the importance of identifying and addressing issues related to device variability, scalability, and system integration in the co-design of devices, circuits, and algorithms.

Memristive devices are currently explored for neuromorphic and emerging unconventional computing concepts towards future low-power computing systems.  These devices have been proposed as: (i) computing elements to support in memory computing in neural networks, (ii) building blocks to reproduce in hardware synaptic or neural functionalities, and (iii) key elements to build nonlinear dynamical circuits. In this framework, both volatile and non-volatile resistance switching memristive devices are widely studied to engineer various computing functions [1].

This talk will present our recent results in the field of volatile electrochemical memristors based on the Ag/SiO_x/Pt structure and how to implement neuromorphic functionalities such as short-term plasticity, paired-pulse facilitation and inhibition, and integrative functions. We will discuss how the interplay between switching times and relaxation effect controls the memristors dynamics and possible various switching modes that can be used to reproduce key synaptic and neuronal functions [2].

The second part of the talk will discuss an unconventional computing approach based on analogue Pt/HfO₂/TiN RRAM devices. We exploit the programmable nonlinearity of the non-volatile memristors to build an analogue nonlinear dynamical circuit based on the Murali- Lakshmanan-Chua (MLC) architecture [3]. The circuit can be tuned from periodic to chaotic behavior through the modulation of an input signal. We demonstrate its processing ability in an approach based on single-node reservoir for various nonlinear classification tasks.

In the era of artificial intelligence (AI), the advancement of deep neural network (DNN) algorithms has pushed conventional digital hardware to its limits due to power efficiency constraints [1]. Recently, analog AI hardware, consisting of crossbar arrays of resistive memory devices, has garnered significant attention as a promising solution to overcome the inherent bottleneck of the von Neumann architecture [2]. These systems enable a more efficient mapping of neural network architectures to hardware, with resistive devices representing the weights. Here, resistive memory (ReRAM) technology, in a crossbar array configuration, play a crucial role in realizing analog AI hardware [3]. ReRAM devices store synaptic weights as conductance values, while the crossbar array physically implements the synaptic interconnect on real hardware. Thanks to its design compatibility with the neural network structure, the ReRAM-based crossbar array can accelerate NN inference as well as deep learning through parallel information processing and weight updating within the memory [4]. This presentation introduces conductive-metal-oxide/HfOx ReRAM technology for DNN hardware accelerators and explores the opportunities presented by both the devices and arrays in the system.

Neuromorphic hardware systems emulate the parallel neural networks of the human brain, and synaptic weight storage elements are crucial for enabling energy-efficient information processing. They must represent multiple data states and be able to be updated analogously. In order to realize highly controllable synaptic devices, replacing the high-k gate dielectric in conventional transistor structures with either solid-electrolytes that facilitate bulk ionic motion or ferroelectric oxide allows for steady adjustment of channel currents in response to gate-voltage signals. This approach, in turn, accelerates backpropagation algorithms used for training neural networks. Furthermore, because the channel current in electrochemical random-access memory (ECRAM) is influenced by the number of mobile ions (e.g., Li or Cu cations) passing through the electrolytes, these synaptic device candidates have demonstrated an excellent linear and symmetrical channel current response when updated using an identical pulse scheme. In the latter case, which is known as the ferroelectric field-effect transistor (FeFET), the number of electrons accumulated near the channel rapidly varies with the degree of the alignment of internal dipoles in thin doped ferroelectric HfO₂. This leads to a multilevel state. Based on the working principles of these two promising candidates, enabling gate-controlled ion-transport primarily in electrolytes for ECRAM and understanding the relationship between polarization and the ferroelectric layer in FeFETs are crucial to improve their properties. Therefore, this study aims to present our recent advances, highlighting the engineering approaches and experimental findings related to ECRAM and FeFET for three-terminal synaptic devices.  

Amorphous oxide semiconductor (AOS) technology has emerged as a transformative platform for the development of advanced memory and logic devices, particularly in the field of flexible electronics. This talk will explore the evolution of AOS-based devices, from Thin-Film Transistors (TFTs) to Resistive switching RAMs (RRAMs), and their integration into a range of computing paradigms. AOS materials, such as Indium Gallium Zinc Oxide (IGZO), offer unique properties like high mobility, low temperature processing, and excellent flexibility, making them ideal for next-generation electronics. We will first examine the capabilities of IGZO TFTs, which have demonstrated remarkable performance in various display, sensor, and neuromorphic applications, highlighting their role as efficient access transistors in RRAMs crossbar arrays. Next, we will discuss the transition to RRAMs and how these devices exploit the resistive switching mechanism for non-volatile memory, enabling high-speed, low-power data storage. The advantages of RRAM technology, including its scalability, endurance, and energy efficiency, will be emphasized, particularly in the context of emerging neuromorphic computing systems such as Reservoir computing (RC). We also discuss the integration of AOS-based RRAMs into flexible and wearable electronics, highlighting their potential to revolutionize both conventional and unconventional computing paradigms. The goal of this talk is to provide insights into the progress of AOS-based RRAM technology and to inspire further exploration of its potential to reshape the future of computing, from memory-intensive applications to neuromorphic and AI-driven systems.

According to the advents of big data processing technologies and artificial intelligence (AI) generation, next-generation memristors have been in the spotlight as technologies to overcome the bottleneck limitations of von Neumann. Memristor (memory + resistor) is one of the key elements for high-performance integrated memory and neuromorphic computing applications with low energy consumptions and efficient processing. Among various memristor candidates, halide perovskites (HPs) have been actively studied as potential candidates for these devices due to their unique switching characteristics with low power consumption, simple fabrication, flexible integration compatibility across various sources for scalability, etc. However, there is still a lack of dynamic physical analysis and overviews about operating mechanisms and characteristics of HPs-based memristor and neuromorphic devices, which are essential for future application realization with high performance and accuracy. So here, we overview and outline the various characteristics and operating principles of the HPs-based memristors and the basic neuromorphic devices. First, briefly introduce HPs-based memristors and neuromorphic applications and discuss different switching types /operating mechanisms according to the conducting pathway occurring inside the active HP layer to figure out the beneficial types for the desired memory/neuromorphic device applications. Finally, show the analyze tools and physical dynamic models for the general insight to electrical actuation of the memory/neuromorphic systems from various perspectives.

One of the greatest challenges of modern society is related to energy consumption, dissipation and waste. A prominent example is that of integrated electronics, where power dissipation issues have become one of its greatest challenges. In this talk, I will discuss how to characterize energy dissipation in electronics, like heating in transistors based on 2D materials or in the conductive filaments of resistive random-access memories (RRAM), using spatially resolved thermometry. As the size of materials and devices shrinks to nanometer, atomic, or even quantum scale, it is more challenging to characterize their thermal properties reliably. Scanning thermal microscopy (SThM) is an emerging method to obtain local thermal information of electronic devices by controlling and monitoring probe–sample thermal exchange processes. Gaining thermal insights of our electronics is essential to design energy efficient circuits and understand and optimize ultra-dense data storage.                     

The ionic conductivity of halide perovskite is responsible for a memory effect that can be used in resistive memories.^1,2 The ionic conductivity can be controlled by the dimensionality of the halide perovskite and this is connected to the long-term stability of several optoelectronic devices. In this work, we discuss how the interplay between ion migration and the chemical reactivity with the external contacts is key to maximize the reliability of the devices, to control the working mechanism and to reduce the energy consumption. Conductive and insulating states are formed via migration of halide vacancy and electrochemically active metals. We show that the working mechanism and performance of the memory devices can be tuned and modified from volatile to non-volatile response.³ Several configurations are  evaluated in which structural layers are modified systematically: formulation of the perovskite,⁴ the nature of the buffer layer⁵  and the nature of the metal contact^3,6. We show that in order to efficiently promote migration of metal contact the use of pre-oxidized metals greatly enhance the performance of the memristor and reduces the energy requirements. Overall, we provide solid understanding on the operational mechanism of halide perovskite memristors that has enabled increased stabilities approaching 10⁵ cycles with well separated states of current and further improvements expected.

The ever-growing prevalence of AI and the IoT necessitates substantial increases in power consumption and data storage capacity. Memory storage devices that are fast, power-efficient, and have a high packing density are thereby gaining interest in the data storage industry. Neuromorphic computing (NC) fits resistive random-access memory (RRAM) devices well because of its decision-making and picture-recognition capabilities. A two-terminal resistive switching device based on Cu/CuO/FTO demonstrated excellent non-volatile RRAM appearances with 150 repeatable cycles, LRS and HRS stability in terms of retention is 1,000 s, and durability for 5000 cycles. The device was designed with inspiration from the human biological brain and was able to be synthesized at a low cost by thermal oxidation of Cu. The active material was CuO, with Cu and FTO serving as the top electrode and bottom contact. We investigated these devices' potential applications in neuromorphic computing. In addition, the devices show impressive mimicking abilities, displaying features such as synaptic weight, learning, and forgetting characteristics, spike time-dependent plasticity (STDP), and pulse-paired facilitation (PPF). In addition, the synaptic artificial neural network shows outstanding short-term (STP) and long-term (LTP) potentiation for six cycles in a row. Therefore, the current study on devices based on Cu/CuO/FTO offers a comprehensive analysis of resistive switching based on CuO active materials, which could lead to neuromorphic computing that goes beyond the von Neumann architecture.